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ADT7462
Dynamic VID Functionality
VID Code
The ADT7462 can be configured to monitor up to seven
VR10 requires only six VID lines (see Table 22). Pin 28
should be connected to ground when monitoring VR10 VID
codes. VID6 reports a 0.
VID inputs. The VID code is output on seven lines from the
CPU to tell the power controller what input voltage it
requires. The ADT7462 can monitor the VID code and the
Table 22. VR10 VID CODES
VID Number Pin No.
Voltage
voltage applied to the CPU to ensure that they match within
an acceptable range. This acceptable range is programmable
in the ADT7462.
The VID lines are monitored by the ADT7462, and the
VID code is stored in the VID Value register (0x97), which
can be read back over the SMBus.
VID monitoring is enabled by setting Bit 7 (VIDs) of Pin
Configuration Register 1 (0x10) to 1. See Table 21 and
Table 22 for information on which pin should be connected
VID6
VID5
VID4
VID3
VID2
VID1
VID0
28
32
31
4
3
2
1
Unused,
Connect to GND
12.5 mV
400 mV
200 mV
100 mV
60 mV
25 mV
to each VID line. When VID monitoring is enabled, all seven
pins are automatically configured as VID inputs. It is not
possible to select six pins as VID inputs and use the
remaining pin as an alternate function.
VID Value Register (0x97)
Bit 0 = VID0 (reflects the logic state of Pin 1)
Bit 1 = VID1 (reflects the logic state of Pin 2)
Bit 2 = VID2 (reflects the logic state of Pin 3)
Bit 3 = VID3 (reflects the logic state of Pin 4)
Bit 4 = VID4 (reflects the logic state of Pin 31)
Bit 5 = VID5 (reflects the logic state of Pin 32)
Bit 6 = VID6 (reflects the logic state of Pin 28)
The ADT7462 supports both the VR10 and the VR11
specifications. The default option supports the VR10
specification. To switch to the VR11 specification, set Bit 6
of Configuration Register 0 (0x00) to 1. VR11 is defined as
eight bits; the ADT7462 monitors only seven VID lines (see
Table 21).
Dynamic VID Monitoring
The ADT7462 supports dynamic VID monitoring. The
purpose of the VID code is to tell the voltage controller what
V CCP voltage should be applied to the CPU. The V CCP
voltage applied to the processor changes as the power
requirements of the processor change. The VID is compared
with V CCP1 only. Note that when the VIDs are enabled, the
LSB value for V CCP1 becomes 0.0125 V (see Table 16).
The VID values can represent voltages from 0.8375 V to
1.6 V. The VID code is sampled by the ADT7462 every
11 m s and is stored in Register 0x97. Once the VID code has
been stable (that is, does not change) for 55 m s, the measured
V CCP is then compared with the VID code. The comparison
table used is for either the VR10 or the VR11 specification
(set by Bit 6 of Register 0x00). If the VID code and the
measured V CCP do not match within a certain limit, an
ALERT is generated.
The VID value decoded and the V CCP measurement must
be within a window controlled by the VID high and low
limits. The VID is compared with V CCP1 only. Register 0x78
holds the 4-bit VID high and low limits. The high limit has
Table 21. VR11 VID CODES
VID Number Pin No.
Voltage
a range of 0 mV to 375 mV with a resolution of 25 mV (four
bits). The low limit has a range of 0 mV to ? 187.5 mV with
a resolution of 12.5 mV (four bits). The high limit is used in
VID6
VID5
VID4
VID3
VID2
VID1
VID0
28
32
31
4
3
2
1
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
a greater-than comparison, and the low limit is used in a
less-than-or-equal-to comparison. Note that if both limits
are set to 0x00, because the low limit is less than or equal to
the comparison, an ALERT always results. Therefore, the
minimum value for low limit is 0x01.
If the V CCP voltage measured and the VID code do not
match to within the programmed limit, Status Bit 6 of the
digital status register is set (Register 0xBE). This, in turn,
can generate an ALERT if it is not masked.
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